Studienhandbuch | PR Signal Processing Architectures

Inhalt

Workload	Education level	Study areas	Responsible person	Hours per week	Coordinating university
4,5 ECTS	M1 - Master's programme 1. year	^(*)Informationselektronik	Michael Lunglmayr	3 hpw	Johannes Kepler University Linz

Detailed information

Original study plan

Master's programme Electronics and Information Technology 2025W

Learning Outcomes

Competences
Students are able to implement efficient signal processing architectures in VHDL and test them on FPGA-based prototypes.

Skills	Knowledge
Know and practically apply VHDL language constructs (k1,k2,k3) Write, simulate, and synthesize synthesizable VHDL code for signal processing architectures (k3,k6) Write bit-true fixed-point co-simulations in MATLAB (k3,k6) Perform VHDL synthesis for FPGA development boards (k3,k6)	DSP Arithmetic DSP Hardware: DSPs, FPGAs, and ASICs Fixed-point data types and arithmetic in VHDL CORDIC Algorithm: Theory, Architectures, and Applications Fixed-point effects in digital filtering Low-cost digital filters Multirate signal processing Sigma-delta modulation and oversampling ADCs Numerically controlled oscillators (NCOs) Strobes, stream-based data processing in digital hardware

Criteria for evaluation

Functionality of the individual tasks and ongoing collaboration

Methods

Implementation DSP algorithms on FPGAs, project work supervised by lecturer

Language

German

Study material

Lecture Slides
P. Pirsch, Architekturen der digitalen Signalverarbeitung, B.G. Teubner Stuttgart, 1996.
U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer Verlag, Berlin Heidelberg, 2007

Changing subject?

Further information

Language can be switched to English if requested

Earlier variants

They also cover the requirements of the curriculum (from - to)
489WSIVADSP14: PR Signal Processing Architectures (2014W-2022S)

On-site course
Maximum number of participants	15
Assignment procedure	Assignment according to sequence