[ 289HWDEHWVK20 ] KV Hardware Design using VHDL
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| Workload |
Education level |
Study areas |
Responsible person |
Hours per week |
Coordinating university |
| 3 ECTS |
B3 - Bachelor's programme 3. year |
(*)Informationselektronik |
Timm Ostermann |
2 hpw |
Johannes Kepler University Linz |
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| Detailed information |
| Original study plan |
Bachelor's programme Electronics and Information Technology (ELIT) 2023W |
| Objectives |
An in-depth introduction to vhdl
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| Subject |
- hardware description language
- y-diagram and vhdl
- vhdl coding
- vhdl modeling
- vhdl simulation cycle
- testbench
- synthesis
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| Criteria for evaluation |
oral exam and/or written exam, written exercise report
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| Methods |
lectures and exercises
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| Language |
German |
| Changing subject? |
No |
| Earlier variants |
They also cover the requirements of the curriculum (from - to)
289TEINHEVK17: KV Hardware Design using VHDL (2017W-2020S)
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| On-site course |
| Maximum number of participants |
35 |
| Assignment procedure |
Assignment according to sequence |
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