Inhalt

[ 921CGELVLDK13 ] KV VLSI Design

Versionsauswahl
(*) Unfortunately this information is not available in english.
Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS M - Master's programme Computer Science Harald Pretl 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Computer Science 2021S
Objectives The students master the design of digital circuits using VHDL and have an overview of the design flow from VHDL to the physical implementation in an integrated circuit.
Subject The lab exercises consist of:

  • Introduction to the basics of the design and synthesis of a 16-bit RISC processor core as a full custom IC, based on existing VHDL knowledge.
  • Simulation of the entire system, including timing data.
  • Getting to know a synthesis library and the synthesis tool DesignVision, and the physical implementation in Cadence Innovus.
Criteria for evaluation Grading of the project, test at the end of the semester (oral or written).
Methods Introduction to the topic using a slide presentation, homework, and laboratory appointment to complete the project. Group work is not planned.
Language (*)Deutsch, English if requested.
Study material Lecture notes will be available for download.
Changing subject? No
Corresponding lecture (*)INMAWKVVLSI: KV VLSI-Entwurf (3 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Direct assignment