Inhalt

[ 921COENHWDK19 ] KV Hardware Design

Versionsauswahl
(*) Unfortunately this information is not available in english.
Workload Education level Study areas Responsible person Hours per week Coordinating university
4,5 ECTS M1 - Master's programme 1. year Computer Science Robert Wille 3 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Computer Science 2021S
Objectives Students understand the different target architectures and components of today’s computing devices. They are enabled to specify complete systems, evaluate their design decisions, and synthesize the resulting systems. They are enabled to check their system for correctness and to test them for physical faults.
Subject
  • Target Architectures for HW/SW Systems
  • Allocation, Binding, Scheduling
  • Partitioning
  • Hardware Design
  • Abstraction Levels
  • Hardware Description Languages (VHDL, SystemC)
  • Synthesis
  • Verification
  • Debugging
  • Test
Criteria for evaluation Oral examination
Methods Talks and Exercises
Language English
Study material Courseware
Changing subject? No
Further information www.jku.at/iic/eda/teaching
Corresponding lecture (*)921COENHWDV13: VL Hardware Design (3 ECTS) + 921COENHWDU13: UE Hardware Design (1,5 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Direct assignment