Inhalt

[ 921COENHWDK19 ] KV (*)Hardware Design

Versionsauswahl
(*) Leider ist diese Information in Deutsch nicht verfügbar.
Workload Ausbildungslevel Studienfachbereich VerantwortlicheR Semesterstunden Anbietende Uni
4,5 ECTS M1 - Master 1. Jahr Informatik Daniel Große 3 SSt Johannes Kepler Universität Linz
Detailinformationen
Quellcurriculum Masterstudium Computer Science 2025W
Lernergebnisse
Kompetenzen
(*)Students are able to execute various tasks throughout the hardware design flow, demonstrating both practical skills and theoretical understanding of challenges in circuit and system design.
Fertigkeiten Kenntnisse
(*)
  • Students understand the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using hardware description languages. (K2)
  • They understand the different target architectures and components of today’s computing devices. (K2)
  • They are enabled to specify complete systems, evaluate their design decisions, and synthesize the resulting systems. (K3, K5)
  • They are enabled to check their system for correctness and to test them for physical faults. (K4, K6)
  • They create a small project targeting a circuit and system design problem. (K6)
(*)
  • Design of Systems
  • Electronic Design Automation
  • Target Architectures for HW/SW Systems
  • Allocation, Binding, Scheduling
  • Partitioning
  • Hardware Design Flow
  • Abstraction Levels
  • Hardware Description Languages (VHDL, SystemC)
  • Synthesis
  • Verification
  • Debugging
  • Test
Beurteilungskriterien (*)Oral examination
Lehrmethoden (*)Talks and Exercises
Abhaltungssprache Englisch
Literatur (*)Courseware
Lehrinhalte wechselnd? Nein
Sonstige Informationen (*)For further information see https://ics.jku.at/teaching
Äquivalenzen (*)921COENHWDV13: VL Hardware Design (3 ECTS) + 921COENHWDU13: UE Hardware Design (1,5 ECTS)
Präsenzlehrveranstaltung
Teilungsziffer -
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