Studienhandbuch | KV Hardware Design using VHDL

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[ 289TEINHEVK17 ] KV Hardware Design using VHDL

Versionsauswahl

Es ist eine neuere Version 2023W dieser LV im Curriculum Master's programme Electronics and Information Technology 2024W vorhanden.

Workload	Education level	Study areas	Responsible person	Hours per week	Coordinating university
3 ECTS	B3 - Bachelor's programme 3. year	^(*)Informationselektronik	Robert Wille	2 hpw	Johannes Kepler University Linz

Detailed information
Original study plan	Bachelor's programme Electronics and Information Technology 2017W
Objectives	An in-depth introduction to vhdl
Subject	hardware description language y-diagram and vhdl vhdl coding vhdl modeling vhdl simulation cycle testbench synthesis
Criteria for evaluation	oral exam and/or written exam, written exercise report
Methods	lectures and exercises
Language	German
Changing subject?	No

On-site course
Maximum number of participants	35
Assignment procedure	Assignment according to sequence