[ 921COENHWDV13 ] VL Hardware Design

(*) Unfortunately this information is not available in english.
Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS M1 - Master's programme 1. year Computer Science Robert Wille 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Computer Science 2016W
Objectives Obtaining an overview of the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using the hardware description language VHDL.
  • Design of Systems
  • Target Architectures for HW/SW Systems
  • Allocation, Binding, Scheduling
  • Partitioning
  • Overview: Software Design (Code Generation, Register Allocation)
  • Hardware Design
  • Abstraction Levels
  • Hardware Description Languages (VHDL, SystemC)
  • Synthesis
  • Verification
  • Debugging


Criteria for evaluation Oral examination.
Methods Talks and Exercises
Language English
Study material Courseware.
Changing subject? No
Further information
Corresponding lecture (*)INMIPVOHWEW: VO Hardwareentwurf (3 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Direct assignment