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Workload
Education level
Study areas
Responsible person
Hours per week
Coordinating university
1,5 ECTS
M1 - Master's programme 1. year
Computer Science
Robert Wille
1 hpw
Johannes Kepler University Linz
Detailed information
Original study plan
Master's programme Computer Science 2016W
Objectives
Obtaining an overview of the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using the hardware description language VHDL.
Subject
VHDL
Design flow for FPGA applications
Limitations in digital hardware
Exercises for practical utilization of the newly learned skills
Criteria for evaluation
Exercises
Methods
Students will work on lab assignments and small projects
