[ 921COENHWDV13 ] VL Hardware Design
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| (*) Unfortunately this information is not available in english. |
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| Workload |
Education level |
Study areas |
Responsible person |
Hours per week |
Coordinating university |
| 3 ECTS |
M1 - Master's programme 1. year |
Computer Science |
Robert Wille |
2 hpw |
Johannes Kepler University Linz |
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| Detailed information |
| Original study plan |
Master's programme Computer Science 2016W |
| Objectives |
Obtaining an overview of the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using the hardware description language VHDL.
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| Subject |
- Design of Systems
- Target Architectures for HW/SW Systems
- Allocation, Binding, Scheduling
- Partitioning
- Overview: Software Design (Code Generation, Register Allocation)
- Hardware Design
- Abstraction Levels
- Hardware Description Languages (VHDL, SystemC)
- Synthesis
- Verification
- Debugging
Test
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| Criteria for evaluation |
Oral examination.
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| Methods |
Talks and Exercises
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| Language |
English |
| Study material |
Courseware.
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| Changing subject? |
No |
| Further information |
www.jku.at/iic/cad/teaching
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| Corresponding lecture |
(*)INMIPVOHWEW: VO Hardwareentwurf (3 ECTS)
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| On-site course |
| Maximum number of participants |
- |
| Assignment procedure |
Direct assignment |
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