[ MEMWEPRSHDL ] PR Circuit Design with HDL Lab (Hardware Description Language)

Workload Education level Study areas Responsible person Hours per week Coordinating university
4,5 ECTS M2 - Master's programme 2. year Mechatronics Thomas Bauernfeind 3 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Mechatronics 2015W
Objectives CAD Lab using HDL (hardware description language)
Subject - Use of HDL during circuit design - CAD Lab
Criteria for evaluation grading during lecture, exam
Language German
Changing subject? No
Further information none
On-site course
Maximum number of participants 20
Assignment procedure Assignment according to sequence