[ IEBPIVODHWE ] VL Digital Hardware Design

Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS B3 - Bachelor's programme 3. year Mechatronics Thomas Bauernfeind 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Bachelor's programme Information Electronics 2012W
Objectives In this lecture the design of digital hardware based on a high level languge and synthesis-driven designflow is presented. VHDL as a hardware description language will be taught in detail.

Students should get a basic understanding of the principles of hardware description languages (HDL). The modeling of concurrent systems and hardware structure in VHDL will be presented. The design of fully synchronous digital circuits with VHDL in a synthesis-driven design flow and the modeling of verfication testbenches key aspect of this lecture.
Subject - Introduction to HDLs


  • Concurrency in VHDL

o processes and signals

  • Structural descriptions in VHDL
  • VHDL statements and datatypes
  • Packages, resolved signals
  • File I/O in VHDL

- Introduction to Synthesis

  • Synchronous design
  • Types, operators and statements for synthesis
  • Modelling of registers and memories
  • Packages for synhtesis

- Verilog (in comparison to VHDL)

Criteria for evaluation exam at the end of the lecture
Methods campus based lecture
Language German
Study material Slide set of the lecture
recommended reading: The Designer's Guide to VHDL, Peter J. Ashenden, Morgan Kaufmann, ISBN-13: 978-1-55860-674-6
Changing subject? No
On-site course
Maximum number of participants -
Assignment procedure Assignment according to sequence