[ IEBPIUEDHWE ] UE Digital Hardware Design

Workload Education level Study areas Responsible person Hours per week Coordinating university
1,25 ECTS B3 - Bachelor's programme 3. year Mechatronics Georg Möstl 1 hpw Johannes Kepler University Linz
Detailed information
Original study plan Bachelor's programme Information Electronics 2012W
Objectives Gain competences in the field of developing digital integrated circuits. All levels from modelling down to configuration of an FPGA architecture are covered. Additionally the verification of each step is considered.
Subject All aspects of the development of digital integrated circuits targeting a FPGA architecture are covered.

The first part covers the modelling of circuits by means of the hardware description language VHDL. Focus is put on the practical usage of VHDL. Different concepts and methods are presented and the students gain practical expierence doing several homeworks.

The second part deals with the implementation view, i.e. the tranlation from a VHDL model to a bitfile which can be loaded into an FPGA. This part includes synthesis, map, place&route.

Additionally several verification techniques are presented.

Criteria for evaluation Correction of homeworks, oral and/or written exams

Methods Presentation of theory; practical work in form of homeworks
Language German
Changing subject? No
On-site course
Maximum number of participants 35
Assignment procedure Assignment according to sequence