[ 921CGELVLDK13 ] KV VLSI Design

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Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS M - Master's programme Computer Science Andreas Rauchenecker 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Computer Science 2013W
Objectives An in-depth look at drafting complex digital circuitry via VHDL. Overview of a design flow in the targeted technology ASIC standard cells.
Subject Basic concepts for a draft and syntheses of a 16 bit RISC processor core as a full costum IC based on current VHDL knowledge. Simulation of the whole system with timing data. Introduction to a syntheses library and the tool "DesignVision".
Criteria for evaluation
Language German
Changing subject? No
Corresponding lecture (*)INMAWKVVLSI: KV VLSI-Entwurf (3 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Direct assignment