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[ 489WSDHVLDK22 ] KV VLSI Design
Versionsauswahl
(*) Unfortunately this information is not available in english.
Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS M - Master's programme (*)Informationselektronik Harald Pretl 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Electronics and Information Technology 2025W
Learning Outcomes
Competences
Based on existing VHDL knowledge, students can design, simulate and synthesize complex digital hardware in a self-responsible and independent manner, and finally realize it as a full-custom IC.
Skills Knowledge
  • Design complex digital hardware using important modelling guidelines for ASIC design and thus optimize the synthesis result (K6)
  • Verify the design through pre-synthesis, post-synthesis and post-layout simulations (K3)
  • Synthesize and implement the design as a full-custom IC and check the timing data (K5)
  • Describe the digital hardware in the design to ensure complete and efficient testing after the physical implementation (K3)
  • Implement a 16-bit RISC processor core as a full-custom IC and verify it with simulations (K5)

Write a documentation for the implementation and the test of the design (K3)

  • Modelling guidelines in ASIC design
  • Synthesis libraries
  • Timing libraries
  • Design for test
  • Digital design flow including tools (Synopsys DesignVision, Cadence Innovus, OpenROAD)
  • Introduction to the basics of the design and realization of a 16-bit RISC processor core as a full-custom IC
  • Simulation of the entire system, including timing data
Criteria for evaluation Grading of the project, exam at the end of the semester (oral or written).
Methods Introduction to the topic using a slide presentation, homework, and laboratory appointments to complete the project. Group work is not planned.
Language English
Study material Lecture notes will be available for download.
Changing subject? No
Further information Basic knowledge of VHDL and hardware design is required.
Corresponding lecture (*)INMAWKVVLSI: KV VLSI-Entwurf (3 ECTS)
Earlier variants They also cover the requirements of the curriculum (from - to)
921CGELVLDK13: KV VLSI Design (2013W-2022S)
On-site course
Maximum number of participants -
Assignment procedure Assignment according to sequence