Inhalt

[ 289HWDEHWVK20 ] KV Hardware Design using HDL

Versionsauswahl
Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS B3 - Bachelor's programme 3. year (*)Informationselektronik Timm Ostermann 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Bachelor's programme Electronics and Information Technology 2025W
Learning Outcomes
Competences
Students understand the basics of digital hardware design with hardware description languages, are able to apply HDLs and independently design digital hardware with the HDLs they have learned.
Skills Knowledge
Understanding of the basics of digital hardware design with hardware description languages (k1-k4), ability to apply the learned HDL (k1-k4), design of hardware by using HDL (k1-k6)
  • hardware description language
  • y-diagram and vhdl
  • vhdl coding
  • vhdl modeling
  • vhdl simulation cycle
  • testbench
  • synthesis
Criteria for evaluation written and/or oral exam, Assessment of exercise sheets.
Methods Slide presentation; joint discussion and independent processing of examples
Language German
Study material Study material is available for download.
Changing subject? No
Earlier variants They also cover the requirements of the curriculum (from - to)
289TEINHEVK17: KV Hardware Design using VHDL (2017W-2020S)
On-site course
Maximum number of participants 35
Assignment procedure Assignment according to sequence