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[ 921COENHWDK19 ] KV Hardware Design
Versionsauswahl
Workload Education level Study areas Responsible person Hours per week Coordinating university
4,5 ECTS M1 - Master's programme 1. year Computer Science Daniel Große 3 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Computer Science 2025W
Learning Outcomes
Competences
Students are able to execute various tasks throughout the hardware design flow, demonstrating both practical skills and theoretical understanding of challenges in circuit and system design.
Skills Knowledge
  • Students understand the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using hardware description languages. (K2)
  • They understand the different target architectures and components of today’s computing devices. (K2)
  • They are enabled to specify complete systems, evaluate their design decisions, and synthesize the resulting systems. (K3, K5)
  • They are enabled to check their system for correctness and to test them for physical faults. (K4, K6)
  • They create a small project targeting a circuit and system design problem. (K6)
  • Design of Systems
  • Electronic Design Automation
  • Target Architectures for HW/SW Systems
  • Allocation, Binding, Scheduling
  • Partitioning
  • Hardware Design Flow
  • Abstraction Levels
  • Hardware Description Languages (VHDL, SystemC)
  • Synthesis
  • Verification
  • Debugging
  • Test
Criteria for evaluation Oral examination
Methods Talks and Exercises
Language English
Study material Courseware
Changing subject? No
Further information For further information see https://ics.jku.at/teaching
Corresponding lecture 921COENHWDV13: VL Hardware Design (3 ECTS) + 921COENHWDU13: UE Hardware Design (1,5 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Direct assignment