| Detailinformationen |
| Quellcurriculum |
Masterstudium Elektronik und Informationstechnik (ELIT) 2023W |
| Ziele |
(*)The students master the design of digital circuits using VHDL and have an overview of the design flow from VHDL to the physical implementation in an integrated circuit.
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| Lehrinhalte |
(*)The lab exercises consist of:
- Introduction to the basics of the design and synthesis of a 16-bit RISC processor core as a full custom IC, based on existing VHDL knowledge.
- Simulation of the entire system, including timing data.
- Getting to know a synthesis library and the synthesis tool DesignVision, and the physical implementation in Cadence Innovus.
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| Beurteilungskriterien |
(*)Grading of the project, test at the end of the semester (oral or written).
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| Lehrmethoden |
(*)Introduction to the topic using a slide presentation, homework, and laboratory appointment to complete the project. Group work is not planned.
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| Abhaltungssprache |
Deutsch |
| Literatur |
(*)Lecture notes will be available for download.
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| Lehrinhalte wechselnd? |
Nein |
| Äquivalenzen |
INMAWKVVLSI: KV VLSI-Entwurf (3 ECTS)
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| Frühere Varianten |
Decken ebenfalls die Anforderungen des Curriculums ab (von - bis)
921CGELVLDK13: KV VLSI Design (2013W-2022S)
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