Studienhandbuch | KV Hardware Design using VHDL

Inhalt

Workload	Education level	Study areas	Responsible person	Hours per week	Coordinating university
3 ECTS	B3 - Bachelor's programme 3. year	^(*)Informationselektronik	Timm Ostermann	2 hpw	Johannes Kepler University Linz

Detailed information
Original study plan	Bachelor's programme Electronics and Information Technology (ELIT) 2023W
Objectives	An in-depth introduction to vhdl
Subject	hardware description language y-diagram and vhdl vhdl coding vhdl modeling vhdl simulation cycle testbench synthesis
Criteria for evaluation	oral exam and/or written exam, written exercise report
Methods	lectures and exercises
Language	German
Changing subject?	No
Earlier variants	They also cover the requirements of the curriculum (from - to) 289TEINHEVK17: KV Hardware Design using VHDL (2017W-2020S)

On-site course
Maximum number of participants	35
Assignment procedure	Assignment according to sequence