[ 289HWDEETIK20 ] KV Introduction to Digital System Design
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| (*) Unfortunately this information is not available in english. |
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| Workload |
Education level |
Study areas |
Responsible person |
Hours per week |
Coordinating university |
| 3 ECTS |
B1 - Bachelor's programme 1. year |
(*)Informationselektronik |
Timm Ostermann |
2 hpw |
Johannes Kepler University Linz |
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| Detailed information |
| Original study plan |
Bachelor's programme Electronics and Information Technology 2020W |
| Objectives |
The lecture provides an overview of digital circuit design.
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| Subject |
- Number system, KV diagram, minimization
- Gate and Flipflops
- Timing
- FSM
- Digital design/ASIC-Design
- Memory
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| Criteria for evaluation |
written and/or oral exam
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| Methods |
Slide presentation; joint discussion of examples
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| Language |
German |
| Study material |
Will be announced in the lecture
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| Changing subject? |
No |
| Corresponding lecture |
(*)MEBWAVOTINF: VO Technische Informatik (3 ECTS)
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| On-site course |
| Maximum number of participants |
35 |
| Assignment procedure |
Assignment according to sequence |
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