[ 289HWDEHDPP20 ] PR Hardware Design Lab

Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS B2 - Bachelor's programme 2. year (*)Informationselektronik Michael Lunglmayr 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Bachelor's programme Electronics and Information Technology 2022W
Objectives Students know and understand the principles of analog and digital hardware design, especially synchronous sequential design (digital) and manual design and calculation of analog circuits as well as analog circuit simulation and subsequent optimization. Students know and are proficient in VHDL simulation and synthesis for FPGAs. They are proficient in validating the function and in debugging analog and digital hardware.
  • Principles of digital hardware design in VHDL and principles of analog hardware design
  • Hands-on VHDL simulation and synthesis for FPGAs
  • Analog design with examples
  • Design and implementation of an analog-to-digital converter
  • Use of interface devices analog/digital
  • Testing and measurements
  • Implementation of final project by system integration of the components developed during the semester
Criteria for evaluation Submitted reports and oral exams
Methods VHDL Introduction at the beginning of the course, introduction by the course instructors, solving of the course problems by the students supported by the course instructors, homework exercises
Language (*)Deutsch, bei Bedarf Englisch
Study material Course material that will be provided
Changing subject? No
On-site course
Maximum number of participants 20
Assignment procedure Assignment according to sequence