[ 921COENHWDK19 ] KV (*)Hardware Design
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| Workload |
Ausbildungslevel |
Studienfachbereich |
VerantwortlicheR |
Semesterstunden |
Anbietende Uni |
| 4,5 ECTS |
M1 - Master 1. Jahr |
Informatik |
Daniel Große |
3 SSt |
Johannes Kepler Universität Linz |
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| Detailinformationen |
| Quellcurriculum |
Masterstudium Computer Science 2021W |
| Ziele |
(*)Students understand the different target architectures and components of today’s computing devices. They are enabled to specify complete systems, evaluate their design decisions, and synthesize the resulting systems. They are enabled to check their system for correctness and to test them for physical faults.
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| Lehrinhalte |
(*)- Target Architectures for HW/SW Systems
- Allocation, Binding, Scheduling
- Partitioning
- Hardware Design
- Abstraction Levels
- Hardware Description Languages (VHDL, SystemC)
- Synthesis
- Verification
- Debugging
- Test
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| Beurteilungskriterien |
(*)Oral examination
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| Lehrmethoden |
(*)Talks and Exercises
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| Abhaltungssprache |
Englisch |
| Literatur |
(*)Courseware
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| Lehrinhalte wechselnd? |
Nein |
| Sonstige Informationen |
(*)https://www.ics.jku.at/teaching/
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| Äquivalenzen |
(*)921COENHWDV13: VL Hardware Design (3 ECTS) + 921COENHWDU13: UE Hardware Design (1,5 ECTS)
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| Präsenzlehrveranstaltung |
| Teilungsziffer |
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| Zuteilungsverfahren |
Direktzuteilung |
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