Study guide of JKU Linz
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KUSSS
Auwea NG
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Electronics and Information Technology (ELIT)
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Electives
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ELIT Specialization
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Integrated Circuit Design
Inhalt
[
489WSESEIUV22
]
VL
Design of Integrated A/D-Converter
Versionsauswahl
Version
2025W
2023W
2022W
Es ist eine neuere Version
2025W
dieser LV im Curriculum Master's programme Electronics and Information Technology 2026W vorhanden.
Workload
Education level
Study areas
Responsible person
Hours per week
Coordinating university
3 ECTS
M - Master's programme
(*)
Informationselektronik
Timm Ostermann
2 hpw
Johannes Kepler University Linz
Detailed information
Original study plan
Master's programme Electronics and Information Technology 2021W
Objectives
Design of integrated sigma-delta ADCs
Subject
system design
different topologies
stability
discrete time/continuous time
building block specification
circuit design
Criteria for evaluation
exam at the end of the lecture
Language
German
Changing subject?
No
Further information
Until term 2022S known as: MEMWEVOEIAD VO Design of Integrated A/D-Converter
Earlier variants
They also cover the requirements of the curriculum (from - to)
MEMWEVOEIAD: VO Design of Integrated A/D-Converter (2004S-2022S)
On-site course
Maximum number of participants
-
Assignment procedure
Assignment according to sequence
