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[ 489WSESMSTV22 ] VL Modelling, simulation and test of integrated circuits
Versionsauswahl
(*) Unfortunately this information is not available in english.
Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS M2 - Master's programme 2. year (*)Informationselektronik Timm Ostermann 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Electronics and Information Technology (ELIT) 2023W
Objectives The lecture provides a (detailed) presentation of modeling, simulation and test techniques of Integrated Circuits.
Subject 
    Model concepts
    Model structure
    Validity
    Simulation 
    Test Basics
    Scan Path Design
    BIST
    BSI
    Analog/RF Test
Criteria for evaluation written and/or oral exam
Methods Slide presentation
Language German
Study material Will be announced in the lecture
Changing subject? No
Corresponding lecture (*)489WSATTISV16: VO Test Integrierter Schaltungen (3 ECTS) oder 489WSATMSSV16: VO Modellierung und Simulation von elektronischen Schaltungen (3 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Assignment according to sequence