[ 921CGELVLDK13 ] KV (*)VLSI Design

(*) Leider ist diese Information in Deutsch nicht verfügbar.
Workload Ausbildungslevel Studienfachbereich VerantwortlicheR Semesterstunden Anbietende Uni
3 ECTS M - Master Informatik Harald Pretl 2 SSt Johannes Kepler Universität Linz
Quellcurriculum Masterstudium Computer Science 2021W
Ziele (*)The students master the design of digital circuits using VHDL and have an overview of the design flow from VHDL to the physical implementation in an integrated circuit.
Lehrinhalte (*)The lab exercises consist of:

  • Introduction to the basics of the design and synthesis of a 16-bit RISC processor core as a full custom IC, based on existing VHDL knowledge.
  • Simulation of the entire system, including timing data.
  • Getting to know a synthesis library and the synthesis tool DesignVision, and the physical implementation in Cadence Innovus.
Beurteilungskriterien (*)Grading of the project, test at the end of the semester (oral or written).
Lehrmethoden (*)Introduction to the topic using a slide presentation, homework, and laboratory appointment to complete the project. Group work is not planned.
Abhaltungssprache Deutsch
Literatur (*)Lecture notes will be available for download.
Lehrinhalte wechselnd? Nein
Äquivalenzen (*)INMAWKVVLSI: KV VLSI-Entwurf (3 ECTS)
Teilungsziffer -
Zuteilungsverfahren Direktzuteilung