Inhalt

[ 289HWDEHDPP20 ] PR Hardware Design Lab

Versionsauswahl
Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS B2 - Bachelor's programme 2. year (*)Informationselektronik Michael Lunglmayr 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Bachelor's programme Electronics and Information Technology 2020W
Objectives
  • Practical implementation of analog/digital hardware designs
  • VHDL simulation and synthesis for FPGAs
  • Being able to do simple testing and debugging of analog/digital hardware
Subject
  • Hands-on VHDL simulation and synthesis for FPGAs
  • Analog design with simple examples
  • Use of simple interface devices analog/digital
  • Testing and measurements
  • Implementation of a final project by connecting the components developed during the semester
Criteria for evaluation Written exercises and oral exams
Methods Introduction by the course instructors, solving of the course problems by the students supported by the course instructors, homework exercises
Language (*)Deutsch, bei Bedarf Englisch
Study material A literature list will be announced at the beginning of the course
Changing subject? No
On-site course
Maximum number of participants 20
Assignment procedure Assignment according to sequence