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[ MEBWAVOTINF ] VL Introduction in Digital System Design
Versionsauswahl
(*) Unfortunately this information is not available in english.
Workload Education level Study areas Responsible person Hours per week Coordinating university
3 ECTS B3 - Bachelor's programme 3. year Mechatronics Timm Ostermann 2 hpw Johannes Kepler University Linz
Detailed information
Original study plan Bachelor's programme Mechatronics 2015W
Objectives Digital design, ASIC design, memory
Subject
  • Number system, KV diagram, minimization
  • Gate and Flipflops
  • Timing
  • FSM
  • Digital design/ASIC-Design
  • Memory
Criteria for evaluation exam at the end of the lecture
Methods Theory and realisation
Language German
Changing subject? No
Further information none
Corresponding lecture (*)ME1PEVOTIFM: VO Technische Informatik für die Mechatronik (3 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Assignment according to sequence