Menü
Positionsanzeige
Inhalt

[ 921COENHWDK19 ] KV Hardware Design
Versionsauswahl
Es ist eine neuere Version 2021W dieser LV im Curriculum Master's programme Business Informatics 2023W vorhanden.
(*) Unfortunately this information is not available in english.
Workload Education level Study areas Responsible person Hours per week Coordinating university
4,5 ECTS M1 - Master's programme 1. year Computer Science Robert Wille 3 hpw Johannes Kepler University Linz
Detailed information
Original study plan Master's programme Computer Science 2019W
Objectives
  • Obtaining an overview of the main steps in the design of circuits and systems as well as receiving basic knowledge in digital chip design using the hardware description language VHDL
  • Obtaining basic knowledge in digital chip design. Acquisition of a hardware description language (VHDL)
Subject
  • Design of Systems
  • Target Architectures for HW/SW Systems
  • Allocation, Binding, Scheduling
  • Partitioning
  • Overview: Software Design (Code Generation, Register Allocation)
  • Hardware Design
  • Abstraction Levels
  • Hardware Description Languages (VHDL, SystemC)
  • Synthesis
  • Verification
  • Debugging
  • Test
  • VHDL
  • Design flow for FPGA applications
  • Limitations in digital hardware
  • Exercises for practical utilization of the newly learned skills
Criteria for evaluation Oral examination
Methods Talks and Exercises
Language English
Study material Courseware
Changing subject? No
Further information www.jku.at/iic/eda/teaching
Corresponding lecture (*)921COENHWDV13: VL Hardware Design (3 ECTS) + 921COENHWDU13: UE Hardware Design (1,5 ECTS)
On-site course
Maximum number of participants -
Assignment procedure Direct assignment